1. Field of the Invention
The present invention relates to the emulation of software written for a given computer on a different computer which executes a different set of instructions; and more particularly to a system for decoding guest instructions into host instructions by the host computer.
2. Description of the Related Art
Central processing units for computers are designed to execute a specific set of instructions unique to a particular central processing unit. Thus, a microprocessor in one family, such as the Motorola 68000 family, executes software written in a language unique to the 68000 family, while processors in the Intel 80286 family execute software written with another language which is unique to that family of processors. A need often arises to execute software written for a particular processor in a host processor that utilizes a different language. For the purposes of this application, the language for the host CPU is based on "host instructions", while the language for other CPUs are referred to as "guest instructions".
Because of the large body of software written for existing processors, such as the Motorola 68000 series, new processors which are designed often attempt to emulate the 68000 series processors in software. This emulation process involves first decoding the 68000 series guest instructions into a sequence of host instructions which accomplish the result intended by the guest instruction. The routines needed to emulate a given instruction are stored in a host addressable table. For instance, in one prior art system, each guest instruction is used to generate a jump table pointer which points to a table that includes one entry for each of the possible combinations of operational code and addressing mode for a guest instruction. The jump table stores a pointer to the particular code segment adapted to a particular code combination. See, ARRANGEMENT FOR SOFTWARE EMULATION, International Application No. PCT/GB87/00202; invented by MacGregor.
A disadvantage of this prior art technique arises because of the delay involved in composing a jump table pointer based on the guest instruction, looking up a second pointer in the jump table, and then accessing the emulation segment. Because of data access latencies and the like, this can significantly slow down the emulation routine.
Accordingly, it is desirable to provide an emulation system which enhances the performance of the host processor in emulation of guest instructions.